公开(公告)号：US20140281643A1

公开(公告)日：2014-09-18

申请号：US13801375

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Kris TIRI ,  Matthew Scott McGregor ,  Yucong Tao

IPC: G06F21/50

CPC classification number: G06F21/57 ,  G06F1/04 ,  G06F1/06 ,  G06F11/0721 ,  G06F11/076 ,  G06F21/00 ,  G06F21/55 ,  G06F21/602 ,  G06F21/70 ,  G06F21/71 ,  G06F21/725

Abstract: Disclosed is a method for detecting clock tampering. In the method a plurality of resettable delay line segments are provided. Resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times. A monotone signal is provided during a clock evaluate time period associated with a clock. The monotone signal is delayed using each of the plurality of resettable delay line segments to generate a respective plurality of delayed monotone signals. The clock is used to trigger an evaluate circuit that uses the plurality of delayed monotone signals to detect a clock fault.

Abstract translation: 公开了一种检测时钟篡改的方法。 在该方法中，提供多个可复位延迟线段。 在与最小延迟时间相关联的可复位延迟线段与与最大延迟时间相关联的可复位延迟线段之间的可复位延迟线段分别与离散增加的延迟时间相关联。 在与时钟相关联的时钟评估时间段期间提供单调信号。 使用多个可复位延迟线段中的每一个来延迟单调信号以产生相应的多个延迟单调信号。 时钟用于触发使用多个延迟单调信号来检测时钟故障的评估电路。

公开(公告)号：US09607153B2

公开(公告)日：2017-03-28

申请号：US13801375

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Kris Tiri ,  Matthew Scott McGregor ,  Yucong Tao

IPC: G06F11/30 ,  G06F1/00 ,  H04L29/06 ,  G06F11/00 ,  G06F21/57 ,  G06F1/06 ,  G06F1/04 ,  G06F11/07 ,  G06F21/72 ,  G06F21/55 ,  G06F21/00 ,  G06F21/70 ,  G06F21/60 ,  G06F21/71

CPC classification number: G06F21/57 ,  G06F1/04 ,  G06F1/06 ,  G06F11/0721 ,  G06F11/076 ,  G06F21/00 ,  G06F21/55 ,  G06F21/602 ,  G06F21/70 ,  G06F21/71 ,  G06F21/725

Abstract: Disclosed is a method for detecting clock tampering. In the method a plurality of resettable delay line segments are provided. Resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times. A monotone signal is provided during a clock evaluate time period associated with a clock. The monotone signal is delayed using each of the plurality of resettable delay line segments to generate a respective plurality of delayed monotone signals. The clock is used to trigger an evaluate circuit that uses the plurality of delayed monotone signals to detect a clock fault.