公开(公告)号：US11809220B1

公开(公告)日：2023-11-07

申请号：US17725170

申请日：2022-04-20

Applicant: QUALCOMM INCORPORATED

Inventor： Deepak Kumar Agarwal ,  Kunal Desai ,  Jimit Shah ,  Rakesh Gehalot

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: Error detection and correction (EDAC) logic of a memory subsystem may be monitored for error corrections, with the EDAC logic configured to use a first EDAC level. The number of error corrections made by the EDAC logic while using the first EDAC level during a time interval may be determined. The EDAC logic may be switched from using the first EDAC level to using a second EDAC level when the number of error corrections using the first EDAC level during the time interval exceeds a threshold.