公开(公告)号：US20220028857A1

公开(公告)日：2022-01-27

申请号：US17354910

申请日：2021-06-22

Applicant: POSTECH Research and Business Development Foundation

Inventor： Chang-Ki BAEK ,  Gayoung KIM ,  Byoung-Don KONG ,  Hyangwoo KIM

IPC: H01L27/102 ,  H01L27/108

Abstract: A memory device includes at least one semiconductor layer having a double PN junction, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. In addition, a capacitor-less memory device includes at least one semiconductor layer including a double PN junction, a control gate which contacts the semiconductor layer, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. Methods of operating the memory device and the capacitor-less memory device are also disclosed.