公开(公告)号：US20230376653A1

公开(公告)日：2023-11-23

申请号：US18315904

申请日：2023-05-11

Applicant: MediaTek Inc.

Inventor： Hsin-Chuan Kuo ,  Chia-Wei Chen ,  Yu-Hsiu Lin ,  Kun-Yu Wang ,  Sheng-Tai Tseng ,  Chun-Ku Ting ,  Fang-Ming Yang ,  Yu-Hsien Ku ,  Jen-Wei Lee ,  Ronald Kuo-Hua Ho ,  Chun-Chieh Wang ,  Yi-Ying Liao ,  Tai-Lai Tung ,  Ming-Fang Tsai ,  Chun-Chih Yang ,  Chih-Wei Ko ,  Kun-Chin Huang

IPC: G06F30/27 ,  G06F30/392

CPC classification number: G06F30/27 ,  G06F30/392

Abstract: A neural network is used to place macros on a chip canvas in an integrated circuit (IC) design. The macros are first clustered into multiple macro clusters. Then the neural network generates a probability distribution over locations on a grid and aspect ratios of a macro cluster. The grid represents the chip canvas and is formed by rows and columns of grid cells. The macro cluster is described by at least an area size, aspect ratios, and wire connections. Action masks are generated for respective ones of the aspect ratios to block out a subset of unoccupied grid cells based on design rules that optimize macro placement. Then, by applying the action masks on the probability distribution, a masked probability distribution is generated. Based on the masked probability distribution, a location on the grid is selected for placing the macro cluster with a chosen aspect ratio.