公开(公告)号：US20230100895A1

公开(公告)日：2023-03-30

申请号：US17945115

申请日：2022-09-15

Applicant: MEDIATEK INC.

Inventor： Li-Ren Huang ,  Chia-Yun Cheng ,  Min-Hao Chiu ,  Hsueh-Yen Shen

IPC: H04N19/423 ,  G06F12/08

Abstract: A video processing circuit includes a first buffer and a computation circuit. Before a second one-dimensional processing operation is performed upon a plurality of consecutive blocks in a second direction, the first computation circuit generates a first processing result for each of the plurality of consecutive blocks by performing a first one-dimensional processing operation upon each of the plurality of consecutive blocks in a first direction that is different from the second direction, and further stores a plurality of first processing results of the plurality of consecutive blocks into the first buffer.