公开(公告)号：US20150200565A1

公开(公告)日：2015-07-16

申请号：US14555586

申请日：2014-11-27

Applicant: MEDIATEK INC.

Inventor： Chih-Ching Lin ,  Yi-Ping Kao ,  Chun-Sung Su

IPC: H02J9/00 ,  H02J4/00

CPC classification number: G06F1/3287 ,  G06F1/3234 ,  H01L23/5286 ,  Y02D10/171 ,  Y10T307/305 ,  Y10T307/391

Abstract: The present invention provides an intergrated circuit. The intergrated circuit comprises: a plurality of core power sources; and a plurality of core power domains, coupled to the core power sources, respectively; wherein the core power domains are overlapped with each other.

Abstract translation: 本发明提供一种集成电路。 集成电路包括：多个核心电源; 以及分别耦合到所述核心电源的多个核心电源域; 其中核心功率域彼此重叠。

公开(公告)号：US10776550B1

公开(公告)日：2020-09-15

申请号：US16383650

申请日：2019-04-14

Applicant: MEDIATEK INC.

Inventor： Yi-Feng Chen ,  Chun-Sung Su

IPC: H03K5/13 ,  G06F30/39

Abstract: An integrated circuit includes a path logic and a timing fixing circuit. The path logic is coupled between an output pin of a first circuit and an input pin of a second circuit. The timing fixing circuit has an input pin coupled to the path logic, and is used to adjust a propagation delay of the path logic. The timing fixing circuit introduces no short-circuit current under normal operation.

公开(公告)号：US10048742B2

公开(公告)日：2018-08-14

申请号：US14555586

申请日：2014-11-27

Applicant: MEDIATEK INC.

Inventor： Chih-Ching Lin ,  Yi-Ping Kao ,  Chun-Sung Su

IPC: G06F1/32 ,  H01L23/528

Abstract: The present invention provides an integrated circuit. The integrated circuit comprises: a plurality of core power sources; and a plurality of core power domains, coupled to the core power sources, respectively; wherein the core power domains are overlapped with each other.