Semiconductor layer structure with a thin blocking layer

    公开(公告)号:US12034277B2

    公开(公告)日:2024-07-09

    申请号:US18326465

    申请日:2023-05-31

    CPC classification number: H01S5/3407 H01S5/3425

    Abstract: A semiconductor layer structure may include a substrate, a blocking layer disposed over the substrate, and one or more epitaxial layers disposed over the blocking layer. The blocking layer may have a thickness of between 50 nanometers (nm) and 4000 nm. The blocking layer may be configured to suppress defects from the substrate propagating to the one or more epitaxial layers. The one or more epitaxial layers may include a quantum-well layer that includes a quantum-well intermixing region formed using a high temperature treatment.

    Semiconductor layer structure with a thin blocking layer

    公开(公告)号:US11670913B2

    公开(公告)日:2023-06-06

    申请号:US16947876

    申请日:2020-08-21

    CPC classification number: H01S5/3407 H01S5/3425

    Abstract: A semiconductor layer structure may include a substrate, a blocking layer disposed over the substrate, and one or more epitaxial layers disposed over the blocking layer. The blocking layer may have a thickness of between 50 nanometers (nm) and 4000 nm. The blocking layer may be configured to suppress defects from the substrate propagating to the one or more epitaxial layers. The one or more epitaxial layers may include a quantum-well layer that includes a quantum-well intermixing region formed using a high temperature treatment.

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