公开(公告)号：US09036689B2

公开(公告)日：2015-05-19

申请号：US13740118

申请日：2013-01-11

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Hyeon Min Bae ,  Soon Won Kwon

IPC: H03H7/30 ,  H04L25/03

CPC classification number: H04L25/03891 ,  H04L25/03961 ,  H04L2025/03407

Abstract: A variable-precision distributed arithmetic (VPDA) multi-input multi-output (MIMO) equalizer is presented to reduce the size and dynamic power of 112 Gbps dual-polarization quadrature phase-shift-keying (DP-QPSK) coherent optical communication receivers. The VPDA MIMO equalizer compensates for channel dispersion as well as various non-idealities of a time-interleaved successive approximation register (SAR) based analog-to-digital converter (ADC) simultaneously by using a least mean square (LMS) algorithm. As a result, area-hungry analog domain calibration circuits are not required. In addition, the VPDA MIMO equalizer achieves 45% dynamic power reduction over conventional finite impulse response (FIR) equalizers by utilizing the minimum required resolution for the equalization of each dispersed symbol.

Abstract translation: 提出了一种可变精度分布算法（VPDA）多输入多输出（MIMO）均衡器，以减小112 Gbps双极化正交相移键控（DP-QPSK）相干光通信接收机的大小和动态功耗。 VPDA MIMO均衡器通过使用最小均方（LMS）算法同时补偿时间交错逐次逼近寄存器（SAR）的模数转换器（ADC）的信道色散以及各种非理想性。 因此，不需要占地面积的模拟域校准电路。 此外，VPDA MIMO均衡器通过利用每个分散符号的均衡的最小所需分辨率，实现了比传统有限脉冲响应（FIR）均衡器的45％动态功率降低。