公开(公告)号：US11895218B2

公开(公告)日：2024-02-06

申请号：US17720257

申请日：2022-04-13

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Jaehyouk Choi ,  Suneui Park ,  Seyeon Yoo ,  Seojin Choi ,  Jooeun Bang

IPC: H04L7/033 ,  H03L7/08

CPC classification number: H04L7/033 ,  H03L7/08

Abstract: Proposed are an ultra-low jitter low-power phase-locked loop using a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD) and an operating method thereof. The proposed PG-ILFM PD includes a replica voltage controlled oscillator (R-VCO) configured to cut off the power supply of the R-VCO repeatedly based on a reference signal SREF and a fundamental sampling phase detector (FSPD) configured to receive an output signal SILFM of the R-VCO as a reference signal for sampling and detect a phase error of a main voltage controlled oscillator (M-VCO).