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公开(公告)号:US11895218B2
公开(公告)日:2024-02-06
申请号:US17720257
申请日:2022-04-13
Inventor: Jaehyouk Choi , Suneui Park , Seyeon Yoo , Seojin Choi , Jooeun Bang
Abstract: Proposed are an ultra-low jitter low-power phase-locked loop using a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD) and an operating method thereof. The proposed PG-ILFM PD includes a replica voltage controlled oscillator (R-VCO) configured to cut off the power supply of the R-VCO repeatedly based on a reference signal SREF and a fundamental sampling phase detector (FSPD) configured to receive an output signal SILFM of the R-VCO as a reference signal for sampling and detect a phase error of a main voltage controlled oscillator (M-VCO).
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公开(公告)号:US11271584B2
公开(公告)日:2022-03-08
申请号:US17159197
申请日:2021-01-27
Inventor: Jaehyouk Choi , Taeho Seong , Yongsun Lee , Chanwoong Hwang , Hangi Park
Abstract: Disclosed is an integrated circuit, which includes a DTC block including DTCs, receiving a first reference signal and a first division signal, and outputting a second reference signal and a second division signal based on the first reference signal, the first division signal, and control codes, a TDC comparing phases of the second reference signal and the second division signal and outputting a comparison signal, a digital loop filter filtering the comparison signal, an oscillator generating an output signal based on the filtered comparison signal, a delta-sigma modulator outputting a first signal and a quantized noise signal based on first and second division ratio signals, a divider dividing a frequency of the output signal based on the first signal and outputting the first division signal, and a probability modulator generating the control codes based on the quantized noise signal. Probability density functions of the control codes are time-invariant.
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