公开(公告)号：US20240045588A1

公开(公告)日：2024-02-08

申请号：US18090645

申请日：2022-12-29

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo JUNG ,  Jie ZHANG ,  HANYEOREUM BAE

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0647 ,  G06F3/0679

Abstract: An accelerator includes a processor and a hybrid memory system. The hybrid memory system includes a resistance-based non-volatile memory, a DRAM used as a cache of the resistance-based non-volatile memory, a non-volatile memory controller connected to the resistance-based non-volatile memory and configured to control the DRAM and the resistance-based non-volatile memory, a memory controller configured to process a memory request from the processor and control the DRAM, and a memory channel configured to connect the DRAM, the non-volatile memory controller, and the memory controller.

公开(公告)号：US20210406170A1

公开(公告)日：2021-12-30

申请号：US17304030

申请日：2021-06-14

Applicant: MemRay Corporation ,  Korea Advanced Institute of Science and Technology

Inventor： Myoungsoo JUNG ,  Jie ZHANG

IPC: G06F12/02 ,  G06F12/1045 ,  G06F12/0882 ,  G06F12/0862

Abstract: A processor corresponding to a core of a coprocessor, a cache used as a buffer of the processor, and a flash controller are connected to an interconnect network. The flash controller and a flash memory are connected to a flash network. The flash controller reads or writes target data of a memory request from or to the flash memory.