公开(公告)号：US20250095717A1

公开(公告)日：2025-03-20

申请号：US18683532

申请日：2021-11-16

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Seong Hwan CHO ,  Gi Woo LEE

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C11/4099 ,  H03M1/12

Abstract: The present invention relates to a bitline multi-level voltage sensing circuit for a multi-bit operation of a DRAM including a memory cell that stores data by an operation of a wordline and a bitline, the bitline multi-level voltage sensing circuit comprising: an operational amplifier having a non-inverting input terminal coupled to a precharging voltage line and an inverting input terminal coupled to a bitline through a first switch enabled by a wordline signal; a feedback capacitor formed between an output terminal of the operational amplifier and an inverting input terminal of the operational amplifier; a second switch formed in parallel with the feedback capacitor between the output terminal of the operational amplifier and the inverting input terminal of the operational amplifier and enabled by a precharging signal; and an analog-to-digital converter that converts an output voltage of the output terminal of the operational amplifier into a digital signal.