公开(公告)号：US20040162867A1

公开(公告)日：2004-08-19

申请号：US10782035

申请日：2004-02-19

Applicant: InterDigital Technology Corporation

Inventor： Ryan Samuel Buchert ,  Sharif M. Shahrier ,  Peter Becker

IPC: G06F015/00

CPC classification number: G06F17/144

Abstract: An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.

Abstract translation: 一种用于使用素数因子算法（PFA）对由CDMA接收机接收的中间码片值的选择数目P进行DFT处理的装置和方法，其中P具有多个相对素数因子F，并且DFT处理被分成M个连续 F点DFT处理。 从单个输入端口存储器检索P数据值，并由控制器选择性地置换为并行高速缓存，以使存储在并行寄存器中的相关旋转因子优化因子分解。 经置换的输入在两个或多个并行PFA电路中被考虑，其中包括加法器和乘法器，其被布置成适应任何尺寸的F点DFT。 PFA电路的输出由合并电路处理，准备输出置换到发送到存储器以用于随后的DFT周期的值。

公开(公告)号：US20030195911A1

公开(公告)日：2003-10-16

申请号：US10120971

申请日：2002-04-11

Applicant: InterDigital Technology Corporation

Inventor： Ryan Samuel Buchert ,  Sharif Shahrier ,  Peter Becker

IPC: G06F015/00

CPC classification number: G06F17/144

Abstract: An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.

Abstract translation: 一种用于使用素数因子算法（PFA）对由CDMA接收机接收的中间码片值的选定数目P进行DFT处理的装置和方法，其中P具有多个相对素数因子F，并且DFT处理被分成M个连续 F点DFT处理。 从单个输入端口存储器检索P数据值，并由控制器选择性地置换为并行高速缓存，以使存储在并行寄存器中的相关旋转因子优化因子分解。 经置换的输入在两个或多个并行PFA电路中被考虑，其中包括加法器和乘法器，其被布置成适应任何尺寸的F点DFT。 PFA电路的输出由合并电路处理，准备输出置换到发送到存储器以用于随后的DFT周期的值。