公开(公告)号：US11210020B2

公开(公告)日：2021-12-28

申请号：US16414383

申请日：2019-05-16

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xioa ,  Qiaosha Zou ,  Wei Yang

IPC: G06F3/06 ,  G06F12/0891 ,  G06F12/0888 ,  G06F12/08 ,  G06F12/0879 ,  G06F12/0895

Abstract: A memory access technology applied to a computer system includes a first-level memory, a second-level memory, and a memory controller. The first-level memory is configured to cache data in the second-level memory. A plurality of access requests for accessing different memory blocks has a mapping relationship with a first cache line in the first-level memory, and the memory controller compares tags of the plurality of access requests with a tag of the first cache line in a centralized manner to determine whether the plurality of access requests hit the first-level memory.

公开(公告)号：US20190272122A1

公开(公告)日：2019-09-05

申请号：US16414383

申请日：2019-05-16

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xioa ,  Qiaosha Zou ,  Wei Yang

IPC: G06F3/06 ,  G06F12/0891

Abstract: A memory access technology applied to a computer system includes a first-level memory, a second-level memory, and a memory controller. The first-level memory is configured to cache data in the second-level memory. A plurality of access requests for accessing different memory blocks has a mapping relationship with a first cache line in the first-level memory, and the memory controller compares tags of the plurality of access requests with a tag of the first cache line in a centralized manner to determine whether the plurality of access requests hit the first-level memory.