公开(公告)号：US20110158008A1

公开(公告)日：2011-06-30

申请号：US12883731

申请日：2010-09-16

Applicant: Hisaaki NISHIMURA ,  Katsuhiko Hoya

Inventor： Hisaaki NISHIMURA ,  Katsuhiko Hoya

IPC: G11C7/00

CPC classification number: G11C7/1051 ,  G11C7/1012 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1069

Abstract: According to one embodiment, in a semiconductor storage device, a first internal bus, a second internal bus, and a third internal bus have bus widths decreasing stepwise from a memory cell array side to a data output circuit side. A first selection circuit and a second selection circuit divide the data, which is input via the first or second internal bus, according to a rate of a decrease in bus width in an input and an output, time-divide the divided data, and output the divided data to the second or third internal bus.

Abstract translation: 根据一个实施例，在半导体存储装置中，第一内部总线，第二内部总线和第三内部总线具有从存储单元阵列侧到数据输出电路侧逐步减小的总线宽度。 第一选择电路和第二选择电路根据输入和输出中的总线宽度的减小率，将经由第一或第二内部总线输入的数据除以划分的数据，并输出 分配数据到第二或第三内部总线。