公开(公告)号：US20160092236A1

公开(公告)日：2016-03-31

申请号：US14502901

申请日：2014-09-30

Applicant: Apple Inc.

Inventor： Pradeep Kanapathipaillai ,  Richard F. Russo ,  Sandeep Gupta ,  Conrado Blasco

IPC: G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857

Abstract: A processor includes a mechanism that checks for and flushes only speculative loads and any respective dependent instructions that are younger than an executed wait for event (WEV) instruction, and which also match an address of a store instruction that has been determined to have been executed by a different processor prior to execution of the paired SEV instruction by the different processor. The mechanism may allow speculative loads that do not match the address of any store instruction that has been determined to have been executed by a different processor prior to execution of the paired SEV instruction by the different processor.

Abstract translation: 处理器包括一种机制，其仅检查和刷新推测负载以及比执行的等待事件（WEV）指令更年轻的任何相应的依赖指令，并且还匹配已经被确定已被执行的存储指令的地址 在由不同处理器执行配对SEV指令之前由不同的处理器。 该机制可以允许在由不同的处理器执行配对的SEV指令之前，已经确定已被不同处理器执行的任何存储指令的地址不匹配的推测性负载。