公开(公告)号：US20230384856A1

公开(公告)日：2023-11-30

申请号：US17664999

申请日：2022-05-25

Applicant: Apple Inc.

Inventor： Ping Zhou ,  Nikolai Schlegel ,  Navid Ehsan ,  Zhimin Chen ,  Gerard D. Jennings

IPC: G06F1/3296 ,  G06F13/16

CPC classification number: G06F1/3296 ,  G06F13/1668

Abstract: A processor can include various processing pipelines that perform different data processing operations, with different pipelines having dedicated logic and memory circuits. A power management circuit can determine when to supply power to various pipelines, including the logic and memory circuits of the various pipelines, depending on a current operating mode of the processor. When a memory circuit transitions to a lower power state such as a sleep state, data can be saved to a different memory circuit that is not transitioning to a lower power state, and when the memory circuit is powered up again, the data can be restored from the different memory circuit.

公开(公告)号：US20240241570A1

公开(公告)日：2024-07-18

申请号：US18412195

申请日：2024-01-12

Applicant: Apple Inc.

Inventor： Ping Zhou ,  Nikolai Schlegel ,  Navid Ehsan ,  Zhimin Chen ,  Gerard D. Jennings

IPC: G06F1/3296 ,  G06F13/16

CPC classification number: G06F1/3296 ,  G06F13/1668

Abstract: A processor can include various processing pipelines that perform different data processing operations, with different pipelines having dedicated logic and memory circuits. A power management circuit can determine when to supply power to various pipelines, including the logic and memory circuits of the various pipelines, depending on a current operating mode of the processor. When a memory circuit transitions to a lower power state such as a sleep state, data can be saved to a different memory circuit that is not transitioning to a lower power state, and when the memory circuit is powered up again, the data can be restored from the different memory circuit.

公开(公告)号：US11907043B2

公开(公告)日：2024-02-20

申请号：US17664999

申请日：2022-05-25

Applicant: Apple Inc.

Inventor： Ping Zhou ,  Nikolai Schlegel ,  Navid Ehsan ,  Zhimin Chen ,  Gerard D. Jennings

IPC: G06F1/3296 ,  G06F13/16

CPC classification number: G06F1/3296 ,  G06F13/1668

Abstract: A processor can include various processing pipelines that perform different data processing operations, with different pipelines having dedicated logic and memory circuits. A power management circuit can determine when to supply power to various pipelines, including the logic and memory circuits of the various pipelines, depending on a current operating mode of the processor. When a memory circuit transitions to a lower power state such as a sleep state, data can be saved to a different memory circuit that is not transitioning to a lower power state, and when the memory circuit is powered up again, the data can be restored from the different memory circuit.