公开(公告)号：US20240313788A1

公开(公告)日：2024-09-19

申请号：US18120838

申请日：2023-03-13

Applicant: Apple Inc.

Inventor： Karim M. Megawer ,  Jongmin Park ,  Thomas Mayer

IPC: H03L7/083 ,  H03K5/156 ,  H03L7/081

CPC classification number: H03L7/083 ,  H03K5/1565 ,  H03L7/0818

Abstract: To enhance phase-locked loop (PLL) performance, PLL duty-cycle calibration may be desirable. In some cases, higher reference clock frequency may assist in reducing phase noise and increasing power efficiency of the PLL. A frequency doubler may increase the PLL reference clock frequency, but the duty cycle error in the clock may result in a spur at a clock frequency offset. Low phase noise PLL architectures may include a static phase offset at the PLL input between the reference path and the feedback path, and the static phase offset may vary with PVT, which may limit the accuracy of duty cycle error detection. Correcting for the static phase offset may cause a disturbance at the PLL output. To address the duty cycle error caused by the higher reference clock frequency, a duty cycle calibration loop may be introduced. For the duty cycle calibration loop, phase offset information may be extracted.

公开(公告)号：US20250105814A1

公开(公告)日：2025-03-27

申请号：US18474808

申请日：2023-09-26

Applicant: Apple Inc.

Inventor： Haitao Cheng ,  Karim M. Megawer

IPC: H03H7/01

Abstract: Techniques for isolation between filters using inductive coupling cancellation are disclosed. An apparatus includes a first filter including a first plurality of inductors and a second filter including a second plurality of inductors. The first and second filters are implemented physically adjacent to one another. First and second ones of the first plurality of inductors and a first one of the second plurality of inductors are polarized in a first direction, while a second one of the second plurality of inductors is polarized in a second direction opposite that of the first direction. The second one of the second plurality of inductors is physically adjacent to one of the first and second ones of the first plurality of inductors such that magnetic coupling currents induced into one another are canceled.

公开(公告)号：US20240313789A1

公开(公告)日：2024-09-19

申请号：US18121404

申请日：2023-03-14

Applicant: Apple Inc.

Inventor： Karim M. Megawer ,  Jongmin Park ,  Thomas Mayer

IPC: H03L7/083 ,  H03L7/081 ,  H03L7/195

CPC classification number: H03L7/083 ,  H03L7/0818 ,  H03L7/195

Abstract: This disclosure is directed to PLLs, and, in particular, to enhancing PLL performance via gain calibration. PLL loop gain may vary with respect to process, voltage, and temperature (PVT) variation. To control the PLL loop gain, a gain calibration loop may be implemented. However, calibrating the loop gain by directly measuring the loop gain may be disadvantageous. To reduce or eliminate PLL loop gain variation due to PVT variation, a PLL having a loop gain function that is a function of an input phase offset time with a phase noise performance that remains consistent across PVT variations is disclosed. By determining a relationship between PLL loop gain and phase offset, detecting and calibrating phase offset may result in enhanced calibration of the PLL loop gain, while avoiding the additional difficulty and complexity associated with directly measuring loop gain of a PLL.