公开(公告)号：US20230084736A1

公开(公告)日：2023-03-16

申请号：US17933603

申请日：2022-09-20

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

IPC: G06F12/0862

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

公开(公告)号：US20240176744A1

公开(公告)日：2024-05-30

申请号：US18438111

申请日：2024-02-09

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/6032

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

公开(公告)号：US11880308B2

公开(公告)日：2024-01-23

申请号：US17933603

申请日：2022-09-20

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/6032

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

公开(公告)号：US11487667B1

公开(公告)日：2022-11-01

申请号：US17397429

申请日：2021-08-09

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

IPC: G06F12/0862

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.