Method and apparatus for in-situ on-chip timing

    公开(公告)号:US11764763B1

    公开(公告)日:2023-09-19

    申请号:US17981507

    申请日:2022-11-07

    Applicant: APPLE INC.

    CPC classification number: H03K3/033 H03K3/0315 H03K19/1737

    Abstract: An Integrated Circuit includes a target circuit, first and second logic chains, a feedback path and calibration circuitry. The target circuit includes first and second inputs. The first and second logic chains propagate a signal from a common input point to the first and second inputs of the target circuit, respectively. The feedback path receives the signal from the first or second input and feeds the signal back to the common input point. The calibration circuitry is configured to connect the first input to the feedback path thereby forming a first closed-loop oscillator circuit, and measure a first oscillation frequency of the first closed-loop oscillator circuit, connect the second input to the feedback path, thereby forming a second closed-loop oscillator circuit, and measure a second oscillation frequency of the second closed-loop oscillator circuit, and verify a timing constraint responsively to the first and second oscillating frequencies.

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