公开(公告)号：US06634012B2

公开(公告)日：2003-10-14

申请号：US09395873

申请日：1999-09-14

申请人： John Xiaoxiong Zhong ,  Dian Yang ,  Zheng Zhou ,  Ting Wang

发明人： John Xiaoxiong Zhong ,  Dian Yang ,  Zheng Zhou ,  Ting Wang

IPC分类号： G06F945

CPC分类号： G01R31/318357 ,  G01R31/318364 ,  G06F17/5022

摘要： A method and apparatus for performing design verification is described. In one embodiment, a method for performing design verification includes specifying at least one object that represents at least one signal as a symbol in a design using a first command and instructing a symbolic simulator with the first command to treat the at least one object as a symbol.

摘要翻译： 描述用于执行设计验证的方法和装置。 在一个实施例中，用于执行设计验证的方法包括：使用第一命令在设计中指定至少一个表示至少一个信号的对象作为符号，并且用第一命令指示符号模拟器将该至少一个对象视为 符号。

公开(公告)号：US5469366A

公开(公告)日：1995-11-21

申请号：US124094

申请日：1993-09-20

申请人： Dian Yang ,  Hashain Karampurwala

发明人： Dian Yang ,  Hashain Karampurwala

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A technique is described which is generally directed to providing better delay determination for "nets" (equivalent circuits of point-to-point wiring) in integrated circuit designs on a semiconductor design automation system by adapting general RC-mesh networks representing those "nets" to efficient nodal matrix circuit solver techniques which are not inherently suited to general RC-mesh circuits. This is accomplished by "collapsing" the general RC-mesh network into an RC-tree equivalent circuit (network) which can be solved (simulated) by such nodal matrix techniques, thus determining node voltages and waveforms for each of the nodes of the simplified network. After solving the simplified network, the simplified network is re-expanded into its original RC-mesh form, determining the node voltages and waveforms at the re-expanded nodes thereof (eliminated during the collapse of the network) by applying simple circuit analysis techniques. Once all of the node waveforms have been re-constructed for all nodes of the original RC-mesh network, they can be compared against critical threshold voltages to determine net delays to each node of the network. Method and apparatus are described.

摘要翻译： 描述了一种技术，其通常旨在通过适配表示这些“网络”的一般RC网格网络来在半导体设计自动化系统上的集成电路设计中为“网络”（点对点布线的等效电路）提供更好的延迟确定 对于一般RC网格电路本身并不适用的高效节点矩阵电路求解器技术。 这是通过将通用RC网格网络“折叠”到可以通过这种节点矩阵技术解决（仿真）的RC树等效电路（网络）中实现的，从而确定简化的每个节点的节点电压和波形 网络。 在简化网络解决之后，将简化网络重新扩展为原始的RC网格形式，通过应用简单的电路分析技术，确定其重新扩展节点（网络崩溃期间消除）中的节点电压和波形。 一旦对原始RC网状网络的所有节点重新构造了所有节点波形，则可以将它们与临界阈值电压进行比较，以确定网络每个节点的净延迟。 描述了方法和装置。