- 专利标题: Removal of sampling clock jitter induced in an output signal of an analog-to-digital converter
-
申请号: US15603713申请日: 2017-05-24
-
公开(公告)号: US09954546B2公开(公告)日: 2018-04-24
- 发明人: Bernd Laquai
- 申请人: Advantest Corporation
- 申请人地址: JP Tokyo
- 专利权人: ADVANTEST CORPORATION
- 当前专利权人: ADVANTEST CORPORATION
- 当前专利权人地址: JP Tokyo
- 主分类号: H03M1/08
- IPC分类号: H03M1/08 ; H03M1/10
摘要:
An automated test equipment for analyzing an analog time domain output signal of an electronic device under test includes: an analog-to-digital converter configured for converting an analog time domain signal; a sampling clock configured for producing a clock signal; a time-to-frequency converter configured for converting the digital time domain signal into a digital frequency domain signal so that the digital frequency domain signal is represented by frequency bins; a memory device configured for storing a set of empirically determined operating parameters; and a jitter components removal module for removing jitter components produced by the analog-to-digital converter, wherein the jitter removal module is configured for subtracting the lower spur and the upper spur of each frequency bin of the frequency bins from the digital frequency domain signal so that the cleaned digital frequency domain signal is produced.
公开/授权文献
信息查询