发明授权
- 专利标题: Manufacturing process of wafer level chip package structure having block structure
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申请号: US15484056申请日: 2017-04-10
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公开(公告)号: US09953960B2公开(公告)日: 2018-04-24
- 发明人: Shih-Wen Chou
- 申请人: ChipMOS Technologies Inc.
- 申请人地址: TW Hsinchu
- 专利权人: ChipMOS Technologies Inc.
- 当前专利权人: ChipMOS Technologies Inc.
- 当前专利权人地址: TW Hsinchu
- 代理机构: JCIPRNET
- 优先权: TW104113401A 20150427
- 主分类号: H01L25/065
- IPC分类号: H01L25/065 ; H01L21/56 ; H01L21/78 ; H01L25/00
摘要:
A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.
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