- 专利标题: Method for verifying design rule checks
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申请号: US14669697申请日: 2015-03-26
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公开(公告)号: US09934349B2公开(公告)日: 2018-04-03
- 发明人: Inder Mohan Bhawnani , Ertugrul Demircan , Dwarka Prasad , Douglas M. Reber , Donald E. Smeltzer , Kenneth J. Danti
- 申请人: FREESCALE SEMICONDUCTOR, INC.
- 申请人地址: US TX Austin
- 专利权人: NXP USA, INC.
- 当前专利权人: NXP USA, INC.
- 当前专利权人地址: US TX Austin
- 主分类号: G06F9/455
- IPC分类号: G06F9/455 ; G06F17/50
摘要:
A method for design rule verification is provided. The method comprises: providing a design rule check (DRC) deck based on a design rule manual (DRM) having a plurality of design rules; providing a plurality of primitive objects; creating a plurality of collection objects, each collection object using one or more primitive objects; using the plurality of collection objects, creating a plurality of DRM test cases; assigning names to each of the plurality of DRM test cases, each of the names based on a rule name of the plurality of design rules and on an expected pass or fail indication; and using the plurality of named DRM test cases to verify the DRC deck.
公开/授权文献
- US20160283642A1 METHOD FOR VERIFYING DESIGN RULE CHECKS 公开/授权日:2016-09-29
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