Circuits, devices and methods for achieving small duty cycles in switching regulators. In some embodiments, a method for generating a low duty cycle output voltage can include setting a ramp signal to a first level substantially with a first edge of a clock signal, and ramping the ramp signal from the first level towards a second level such that voltage level of the ramp signal crosses a compensation level, with the ramping beginning at a time before a second edge of the clock signal. The method can further include starting an output pulse substantially with the second edge of the clock signal, and ending the output pulse substantially with an edge of a pulse-width modulation (PWM) signal that results from the ramp signal crossing the compensation level during the ramping.