The present disclosure relates to memory structures and, more particularly, to double bandwidth algorithmic memory array structures and methods of use. The memory array includes: a plurality of memory banks each of which includes addressable storage units; a redundant array of independent disks (RAID) bank which stores parity bits corresponding to data written into any of the plurality of memory banks at a same address; and a plurality of XOR gates in which data written into any of the plurality of memory banks is cascaded therethrough to refresh the parity bits in the RAID bank.