Invention Grant
- Patent Title: Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
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Application No.: US14730030Application Date: 2015-06-03
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Publication No.: US09847324B2Publication Date: 2017-12-19
- Inventor: Yaojian Lin , Kang Chen
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L21/683 ; H01L23/498 ; H01L23/538 ; H01L23/552 ; H01L25/065 ; H01L25/10 ; H01L25/07 ; H01L21/56 ; H01L23/31 ; H01L23/00

Abstract:
A semiconductor device has a temporary carrier. A semiconductor die is oriented with an active surface toward, and mounted to, the temporary carrier. An encapsulant is deposited with a first surface over the temporary carrier and a second surface, opposite the first surface, is deposited over a backside of the semiconductor die. The temporary carrier is removed. A portion of the encapsulant in a periphery of the semiconductor die is removed to form an opening in the first surface of the encapsulant. An interconnect structure is formed over the active surface of the semiconductor die and extends into the opening in the encapsulant layer. A via is formed and extends from the second surface of the encapsulant to the opening. A first bump is formed in the via and electrically connects to the interconnect structure.
Public/Granted literature
- US20150294962A1 Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP Public/Granted day:2015-10-15
Information query
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