- Patent Title: Process for controlling the correct positioning of test probes on terminations of electronic devices integrated on a semiconductor and corresponding electronic device
-
Application No.: US14868904Application Date: 2015-09-29
-
Publication No.: US09823300B2Publication Date: 2017-11-21
- Inventor: Alberto Pagani
- Applicant: STMicroelectronics S.r.l.
- Applicant Address: FR Agrate Brianza
- Assignee: STMicroelectronics S.R.L.
- Current Assignee: STMicroelectronics S.R.L.
- Current Assignee Address: FR Agrate Brianza
- Agency: Gardere Wynne Sewell LLP
- Priority: ITMI2009A2332 20091230
- Main IPC: G01R31/20
- IPC: G01R31/20 ; G01R31/28

Abstract:
An electrical check executed on wafer tests for the correct positioning or alignment of the probes of a probe card on the pads or bumps of the electronic devices integrated on the wafer. A signal is applied to cause a current to circulate in at least part of a seal ring of at least one of the electronic devices. In a case where the current flows between and through multiple electronic devices, the seal rings of those electronic devices are suitably interconnected to each other by electronic structures that extend through the scribe line between electronic devices.
Public/Granted literature
Information query