- 专利标题: Systems and methods for package on package through mold interconnects
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申请号: US14937022申请日: 2015-11-10
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公开(公告)号: US09659908B1公开(公告)日: 2017-05-23
- 发明人: Shubhada H. Sahasrabudhe , Sandeep B Sane , Siddarth Kumar , Shalabh Tandon
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwegman Lundberg & Woessner, P.A.
- 主分类号: H01L25/065
- IPC分类号: H01L25/065 ; H01L23/31 ; H01L23/00 ; H01L25/00 ; H01L21/56
摘要:
Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.
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