According to one embodiment, a semiconductor memory 100 includes a memory cell array 100A composed of a plurality of SRAM cells 10 including NMOS transistors and PMOS transistors, and a bias circuit 100B connected to a ground GND1 or power supply voltage VDD1 of the memory cell array 100A. The bias circuit 100B includes NMOS transistors 121, 122, 133 and 134 that are same as the NMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, and PMOS transistors 111 and 112 that are same as the PMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion. Diffusion regions of the NMOS transistors and the PMOS transistors are formed in a same semiconductor layer.