A system includes first and second failsafe devices. Each of the failsafe devices includes a processor and a memory. The memory stores instructions executable by the processor for performing at least one of detecting a fault and providing a communication concerning a fault. The system further includes an arbitration bus connecting the first and second failsafe devices. The communication concerning the fault may be provided from a first one of the first and second failsafe devices to a second one of the first and second failsafe devices.