Invention Grant
US09547048B2 Circuit and method for reducing an offset component of a plurality of vertical hall elements arranged in a circle
有权
用于减少布置在圆圈中的多个垂直霍尔元件的偏移分量的电路和方法
- Patent Title: Circuit and method for reducing an offset component of a plurality of vertical hall elements arranged in a circle
- Patent Title (中): 用于减少布置在圆圈中的多个垂直霍尔元件的偏移分量的电路和方法
-
Application No.: US14155047Application Date: 2014-01-14
-
Publication No.: US09547048B2Publication Date: 2017-01-17
- Inventor: Hernan D. Romero
- Applicant: Allegro Microsystems, LLC
- Applicant Address: US MA Worcester
- Assignee: Allegro MicoSystems, LLC
- Current Assignee: Allegro MicoSystems, LLC
- Current Assignee Address: US MA Worcester
- Agency: Daly, Crowley, Mofford and Durkee, LLP
- Main IPC: G01B7/30
- IPC: G01B7/30 ; G01B7/14 ; G01R33/06 ; H01L43/06 ; G01R33/00 ; G01R33/07
Abstract:
Output signals from two or more vertical Hall elements arranged in a circle are combined is ways that reduce an offset voltage as the two or more vertical Hall elements are sequenced to generated a sequential output signal.
Public/Granted literature
Information query
