A vertical memory device includes a substrate, gate lines, channels, contacts and contact spacers. The gate lines are stacked on top of each other on the substrate. The gate lines are spaced apart from each other in a vertical direction with respect to a top surface of the substrate. The gate lines include step portions that extend in a parallel direction with respect to the top surface of the substrate. The channels extend through the gate lines in the vertical direction. The contacts are on the step portions of the gate lines. The contact spacers are selectively formed along sidewalls of a portion of the contacts.