A latch circuit that has a dynamic mode and a static mode is provided. Clock signals are generated specifically for a feedback path of a storage circuit in the latch circuit. The generated clock signals include transitions that cause clocked NMOS and PMOS devices in the feedback path to function, and for other input clock frequencies, the generated clock signals do not include transitions that cause the clocked PMOS and NMOS devices to be active, and have states that cause clocked PMOS and NMOS devices to be inactive.