发明授权
- 专利标题: Latch circuit
- 专利标题(中): 锁存电路
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申请号: US14678704申请日: 2015-04-03
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公开(公告)号: US09397642B2公开(公告)日: 2016-07-19
- 发明人: Hae-Rang Choi , Mi-Hyun Hwang
- 申请人: SK hynix Inc.
- 申请人地址: KR Gyeonggi-do
- 专利权人: SK Hynix Inc.
- 当前专利权人: SK Hynix Inc.
- 当前专利权人地址: KR Gyeonggi-do
- 代理机构: IP & T Group LLP
- 优先权: KR10-2014-0174945 20141208
- 主分类号: H03K3/356
- IPC分类号: H03K3/356
摘要:
A latch circuit includes a first PMOS transistor suitable for pull-up driving a second node based on a voltage of a first node, a first NMOS transistor suitable for pull-down driving the second node based on a voltage of the first node, a second PMOS transistor suitable for pull-up driving the first node based on a voltage of the second node, a second NMOS transistor suitable for pull-down driving the first node based on a voltage of the second node, a first separation element suitable for electrically separating the first NMOS transistor from the second node when the first PMOS transistor is turned on, and a second separation element suitable for electrically separating the second NMOS transistor from the first node when the second PMOS transistor is turned on.
公开/授权文献
- US20160164504A1 LATCH CIRCUIT 公开/授权日:2016-06-09
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