发明授权
- 专利标题: Hierarchical write-combining cache coherence
- 专利标题(中): 分层写入组合高速缓存一致性
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申请号: US14010096申请日: 2013-08-26
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公开(公告)号: US09396112B2公开(公告)日: 2016-07-19
- 发明人: Blake A. Hechtman , Bradford M. Beckmann
- 申请人: Advanced Micro Devices, Inc.
- 申请人地址: US CA Sunnyvale
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: US CA Sunnyvale
- 代理机构: Volpe and Koenig, P.C.
- 主分类号: G06F12/08
- IPC分类号: G06F12/08
摘要:
A method, computer program product, and system is described that enforces a release consistency with special accesses sequentially consistent (RCsc) memory model and executes release synchronization instructions such as a StRel event without tracking an outstanding store event through a memory hierarchy, while efficiently using bandwidth resources. What is also described is the decoupling of a store event from an ordering of the store event with respect to a RCsc memory model. The description also includes a set of hierarchical read-only cache and write-only combining buffers that coalesce stores from different parts of the system. In addition, a pool component maintains partial order of received store events and release synchronization events to avoid content addressable memory (CAM) structures, full cache flushes, as well as direct write-throughs to memory. The approach improves the performance of both global and local synchronization events and reduces overhead in maintaining write-only combining buffers.
公开/授权文献
- US20150058567A1 HIERARCHICAL WRITE-COMBINING CACHE COHERENCE 公开/授权日:2015-02-26
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