An aspect of one present embodiment, there is provided a solid state image processer, including a sample-and-hold circuit sampling an output signal of the CCD to hold the output signal of the CCD as voltage, a pre-buffer receiving an output signal of the sample-and-hold circuit, a selection circuit receiving the output signal of the pre-buffer as a first input signal and the output signal of the CCD as a second input signal to select the first input signal or the second input signal as an output signal of the selection circuit according to an instruction of a selection signal, and a main buffer receiving the output signal of the selection circuit.