Invention Grant
US09385102B2 Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
有权
半导体器件及半导体晶片上薄层扇形晶片级芯片级封装中的支撑层的方法
- Patent Title: Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
- Patent Title (中): 半导体器件及半导体晶片上薄层扇形晶片级芯片级封装中的支撑层的方法
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Application No.: US13630912Application Date: 2012-09-28
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Publication No.: US09385102B2Publication Date: 2016-07-05
- Inventor: Yaojian Lin , Kang Chen , Yu Gu
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L23/48 ; H01L23/00 ; H01L23/31 ; H01L21/56 ; H01L23/498

Abstract:
A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer an includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (μm). The thickness of the semiconductor die is at least 1 μm less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.
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