A power converter includes a converter circuit comprising a semiconductor switch configured to couple a power supply node to an output node responsive to an input signal applied to a control terminal thereof. The power converter further includes a slew rate limiter circuit coupled to the control terminal of the semiconductor switch and configured to limit a slew rate of an output voltage at the output node. The semiconductor switch may include a field-effect transistor (FET), the control terminal may include a gate terminal of the FET, and the slew rate limiter circuit may include a capacitor having a capacitance less than a gate-source capacitance of the FET.