Invention Grant
US09201655B2 Method, computer program product, and hardware product for eliminating or reducing operand line crossing penalty
有权
方法,计算机程序产品和硬件产品,用于消除或减少操作线越界处罚
- Patent Title: Method, computer program product, and hardware product for eliminating or reducing operand line crossing penalty
- Patent Title (中): 方法,计算机程序产品和硬件产品,用于消除或减少操作线越界处罚
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Application No.: US12051296Application Date: 2008-03-19
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Publication No.: US09201655B2Publication Date: 2015-12-01
- Inventor: Vimal M. Kapadia , Fadi Y. Busaba , Edward T. Malley , John G. Rell, Jr. , Chung-Lung Kevin Shum
- Applicant: Vimal M. Kapadia , Fadi Y. Busaba , Edward T. Malley , John G. Rell, Jr. , Chung-Lung Kevin Shum
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Margaret McNamara
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/28 ; G06F9/38

Abstract:
Eliminating or reducing an operand line crossing penalty by performing an initial fetch for an operand from a data cache of a processor. The initial fetch is performed by allowing or permitting the initial fetch to occur unaligned with reference to a quadword boundary. A plurality of subsequent fetches for a corresponding plurality of operands from the data cache are performed wherein each of the plurality of subsequent fetches is aligned to any of a plurality of quadword boundaries to prevent each of a plurality of individual fetch requests from spanning a plurality of lines in the data cache. A steady stream of data is maintained by placing an operand buffer at an output of the data cache to store and merge data from the initial fetch and the plurality of subsequent fetches, and to return the stored and merged data to the processor.
Public/Granted literature
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