Invention Grant
- Patent Title: Integrated circuit packages and methods for forming the same
- Patent Title (中): 集成电路封装及其形成方法
-
Application No.: US13529179Application Date: 2012-06-21
-
Publication No.: US09196532B2Publication Date: 2015-11-24
- Inventor: Chia-Wei Tu , Yian-Liang Kuo , Wen-Hsiung Lu , Hsien-Wei Chen , Tsung-Fu Tsai
- Applicant: Chia-Wei Tu , Yian-Liang Kuo , Wen-Hsiung Lu , Hsien-Wei Chen , Tsung-Fu Tsai
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L23/522 ; H01L23/31 ; H01L23/00
Abstract:
A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
Public/Granted literature
- US20130341800A1 Integrated Circuit Packages and Methods for Forming the Same Public/Granted day:2013-12-26
Information query
IPC分类:
