Invention Grant
US09141469B2 Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic
有权
高效和可扩展的循环冗余校验电路使用伽罗瓦域算术
- Patent Title: Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic
- Patent Title (中): 高效和可扩展的循环冗余校验电路使用伽罗瓦域算术
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Application No.: US14083059Application Date: 2013-11-18
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Publication No.: US09141469B2Publication Date: 2015-09-22
- Inventor: Sivakumar Radhakrishnan , Mark A. Schmisseur , Sin S. Tan , Kenneth C. Haren , Thomas C. Brown , Pankaj Kumar , Vinodh Gopal , Wajdi K. Feghali
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/00 ; H03M1/10 ; H03M7/42 ; H03M13/09 ; H03M13/15
Abstract:
Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.
Public/Granted literature
- US20140082451A1 EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS-FIELD ARITHMETIC Public/Granted day:2014-03-20
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