Invention Grant
US09123721B2 Placement of monolithic inter-tier vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace
有权
在单片三维（3D）集成电路（IC）（3DIC）中使用集群放置单层跨层通孔（MIV）以增加可用空格
- Patent Title: Placement of monolithic inter-tier vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace
- Patent Title (中): 在单片三维（3D）集成电路（IC）（3DIC）中使用集群放置单层跨层通孔（MIV）以增加可用空格
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Application No.: US14132098Application Date: 2013-12-18
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Publication No.: US09123721B2Publication Date: 2015-09-01
- Inventor: Kambiz Samadi , Shreepad Amar Panth , Pratyush Kamal , Yang Du
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Withrow & Terranova, PLLC
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522 ; G06F17/50
Abstract:
Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.
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