Invention Grant
- Patent Title: Multi-level instruction cache prefetching
- Patent Title (中): 多级指令缓存预取
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Application No.: US13312962Application Date: 2011-12-06
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Publication No.: US09110810B2Publication Date: 2015-08-18
- Inventor: Nicholas Wang , Jack Hilaire Choquette
- Applicant: Nicholas Wang , Jack Hilaire Choquette
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA CORPORATION
- Current Assignee: NVIDIA CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/28 ; G06F12/08 ; G06F9/38

Abstract:
One embodiment of the present invention sets forth an improved way to prefetch instructions in a multi-level cache. Fetch unit initiates a prefetch operation to transfer one of a set of multiple cache lines, based on a function of a pseudorandom number generator and the sector corresponding to the current instruction L1 cache line. The fetch unit selects a prefetch target from the set of multiple cache lines according to some probability function. If the current instruction L1 cache 370 is located within the first sector of the corresponding L1.5 cache line, then the selected prefetch target is located at a sector within the next L1.5 cache line. The result is that the instruction L1 cache hit rate is improved and instruction fetch latency is reduced, even where the processor consumes instructions in the instruction L1 cache at a fast rate.
Public/Granted literature
- US20130145102A1 MULTI-LEVEL INSTRUCTION CACHE PREFETCHING Public/Granted day:2013-06-06
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