A CMOS device that includes an nFET portion, a pFET portion and an interlayer dielectric between the nFET portion and pFET portion. The nFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer in direct physical contact with the barrier layer and a gate metal filling the remainder of the recess. The pFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer on the barrier layer, a third titanium nitride layer in direct physical contact with the second titanium nitride layer and a gate metal filling the remainder of the recess.