发明授权
US09032348B2 Physics-based reliability model for large-scale CMOS circuit design
有权
基于物理的大规模CMOS电路设计可靠性模型
- 专利标题: Physics-based reliability model for large-scale CMOS circuit design
- 专利标题(中): 基于物理的大规模CMOS电路设计可靠性模型
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申请号: US14100712申请日: 2013-12-09
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公开(公告)号: US09032348B2公开(公告)日: 2015-05-12
- 发明人: Hugh James Barnaby , Ivan Sanchez Esqueda
- 申请人: Arizona Board of Regents on behalf of Arizona State University , University of Southern California
- 申请人地址: US AZ Scottsdale US CA Los Angeles
- 专利权人: Arizona Board of Regents on behalf of Arizona State University,University of Southern California
- 当前专利权人: Arizona Board of Regents on behalf of Arizona State University,University of Southern California
- 当前专利权人地址: US AZ Scottsdale US CA Los Angeles
- 代理机构: Withrow & Terranova, P.L.L.C.
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation effect(s) in a circuit simulation, a simulated defect signal level is produced. More specifically, the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and a simulated input signal level of a simulated input signal. As such, the charge degradation effect(s) are simulated externally with respect to the in silico active semiconductor component. In this manner, the in silico active semiconductor component does not need to be reprogrammed in order to simulate charge degradation effects.
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