发明授权
US09030217B2 Semiconductor wafer and method for auto-calibrating integrated circuit chips using PLL at wafer level
有权
半导体晶片和方法，用于在晶片级使用PLL自动校准集成电路芯片
- 专利标题： Semiconductor wafer and method for auto-calibrating integrated circuit chips using PLL at wafer level
- 专利标题（中）： 半导体晶片和方法，用于在晶片级使用PLL自动校准集成电路芯片
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申请号： US13605554申请日： 2012-09-06
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公开(公告)号： US09030217B2公开(公告)日： 2015-05-12
- 发明人: Hyunseok Kim , Su Na Choi , Heyung Sub Lee , Cheol Sig Pyo
- 申请人： Hyunseok Kim , Su Na Choi , Heyung Sub Lee , Cheol Sig Pyo
- 申请人地址： KR Daejeon
- 专利权人： Electronics and Telecommunications Research Institute
- 当前专利权人： Electronics and Telecommunications Research Institute
- 当前专利权人地址： KR Daejeon
- 代理机构： Rabin & Berdo, P.C.
- 优先权： KR10-2012-0042305 20120423
- 主分类号： G06K19/07
- IPC分类号： G06K19/07
摘要：
In integrated circuit chips that are used for RFID, a method of calibrating an operation frequency that is generated in an operation frequency generator and a semiconductor wafer including a calibration circuit are provided. The method of calibrating an operation frequency of integrated circuit chips includes: supplying DC power to the integrated circuit chips; selecting an integrated circuit chip to perform calibration of an operation frequency; receiving an operation frequency that is generated in the selected integrated circuit chip; calculating a difference between a phase of the operation frequency and a phase of a calibration target frequency; generating a frequency calibration value of the operation frequency using the phase difference; transmitting a control signal including the frequency calibration value to the integrated circuit chip; and releasing a selection of the integrated circuit chip in which calibration of the operation frequency is complete.
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