发明授权
US08909906B2 Packet processor configured for processing features directed by branch instruction with logical operator and two feature selector fields
有权
分组处理器被配置用于处理具有逻辑运算符和两个特征选择器字段的分支指令指向的特征
- 专利标题： Packet processor configured for processing features directed by branch instruction with logical operator and two feature selector fields
- 专利标题（中）： 分组处理器被配置用于处理具有逻辑运算符和两个特征选择器字段的分支指令指向的特征
-
申请号： US12951591申请日： 2010-11-22
-
公开(公告)号： US08909906B2公开(公告)日： 2014-12-09
- 发明人: Hamid Assarpour
- 申请人： Hamid Assarpour
- 申请人地址： US NJ Basking Ridge
- 专利权人： Avaya Inc.
- 当前专利权人： Avaya Inc.
- 当前专利权人地址： US NJ Basking Ridge
- 代理机构： Anderson Gorecki & Rouille LLP
- 主分类号： G06F9/32
- IPC分类号： G06F9/32 ; H04L12/46 ; H04L12/741
摘要：
A method and apparatus for branch reduction in a multithreaded packet processor is presented. An instruction is executed which includes testing of a branch flag. The branch flag references a configuration bit vector wherein each bit in the configuration bit vector corresponds to a respective feature. When said branch flag returns a first result processing is continues at an instruction located at a first location relative to a Program Counter (PC) and when the branch flag returns a second result processing is continued at a second location relative to said PC.
公开/授权文献
信息查询
