Invention Grant
- Patent Title: Reducing settling time in phase-locked loops
- Patent Title (中): 降低锁相环的稳定时间
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Application No.: US13895139Application Date: 2013-05-15
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Publication No.: US08885788B1Publication Date: 2014-11-11
- Inventor: Claudio Rey , David Harnishfeger
- Applicant: Intel IP Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel IP Corporation
- Current Assignee: Intel IP Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Baker Botts L.L.P.
- Main IPC: H03D3/24
- IPC: H03D3/24 ; H03L7/099

Abstract:
A circuit may include a phase detector configured to generate a phase error signal based on a feedback signal and an oscillator configured to generate an output signal. The feedback signal may be based on the output signal. The circuit may also include a determination unit configured to measure a phase of the feedback signal based on the phase error signal when an output of the phase detector and an input of the oscillator are communicatively decoupled. The circuit may also include an adjustment unit configured to subtract the measured phase of the feedback signal from an intermediate signal upon which the output signal is based when the output of the phase detector and the input of the oscillator are communicatively coupled.
Public/Granted literature
- US20140340131A1 REDUCING SETTLING TIME IN PHASE-LOCKED LOOPS Public/Granted day:2014-11-20
Information query
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