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US08884387B2 Pillar-based interconnects for magnetoresistive random access memory 有权
用于磁阻随机存取存储器的基于柱的互连

Pillar-based interconnects for magnetoresistive random access memory
Abstract:
A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.
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